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291 lines
10 KiB
291 lines
10 KiB
/** |
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****************************************************************************** |
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* @file system_stm32l0xx.c |
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* @author MCD Application Team |
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* @version V1.7.1 |
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* @date 25-November-2016 |
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* @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File. |
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* |
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* This file provides two functions and one global variable to be called from |
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* user application: |
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* - SystemInit(): This function is called at startup just after reset and |
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* before branch to main program. This call is made inside |
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* the "startup_stm32l0xx.s" file. |
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* |
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* - SystemCoreClock variable: Contains the core clock (HCLK), it can be used |
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* by the user application to setup the SysTick |
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* timer or configure other parameters. |
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* |
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* - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must |
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* be called whenever the core clock is changed |
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* during program execution. |
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* |
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* |
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****************************************************************************** |
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* @attention |
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* |
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* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
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* |
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* Redistribution and use in source and binary forms, with or without modification, |
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* are permitted provided that the following conditions are met: |
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* 1. Redistributions of source code must retain the above copyright notice, |
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* this list of conditions and the following disclaimer. |
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* 2. Redistributions in binary form must reproduce the above copyright notice, |
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* this list of conditions and the following disclaimer in the documentation |
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* and/or other materials provided with the distribution. |
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* 3. Neither the name of STMicroelectronics nor the names of its contributors |
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* may be used to endorse or promote products derived from this software |
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* without specific prior written permission. |
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* |
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
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* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
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* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
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* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
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* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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* |
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****************************************************************************** |
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*/ |
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/** @addtogroup CMSIS |
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* @{ |
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*/ |
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/** @addtogroup stm32l0xx_system |
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* @{ |
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*/ |
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/** @addtogroup STM32L0xx_System_Private_Includes |
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* @{ |
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*/ |
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#include "stm32l0xx.h" |
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#if !defined (HSE_VALUE) |
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#define HSE_VALUE ((uint32_t)8000000U) /*!< Value of the External oscillator in Hz */ |
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#endif /* HSE_VALUE */ |
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#if !defined (MSI_VALUE) |
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#define MSI_VALUE ((uint32_t)2000000U) /*!< Value of the Internal oscillator in Hz*/ |
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#endif /* MSI_VALUE */ |
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#if !defined (HSI_VALUE) |
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#define HSI_VALUE ((uint32_t)16000000U) /*!< Value of the Internal oscillator in Hz*/ |
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#endif /* HSI_VALUE */ |
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/** |
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* @} |
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*/ |
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/** @addtogroup STM32L0xx_System_Private_TypesDefinitions |
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* @{ |
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*/ |
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/** |
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* @} |
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*/ |
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/** @addtogroup STM32L0xx_System_Private_Defines |
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* @{ |
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*/ |
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/************************* Miscellaneous Configuration ************************/ |
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/*!< Uncomment the following line if you need to relocate your vector Table in |
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Internal SRAM. */ |
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/* #define VECT_TAB_SRAM */ |
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#define VECT_TAB_OFFSET 0x00U /*!< Vector Table base offset field. |
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This value must be a multiple of 0x200. */ |
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/******************************************************************************/ |
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/** |
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* @} |
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*/ |
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/** @addtogroup STM32L0xx_System_Private_Macros |
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* @{ |
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*/ |
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/** |
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* @} |
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*/ |
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/** @addtogroup STM32L0xx_System_Private_Variables |
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* @{ |
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*/ |
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/* This variable is updated in three ways: |
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1) by calling CMSIS function SystemCoreClockUpdate() |
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2) by calling HAL API function HAL_RCC_GetHCLKFreq() |
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3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency |
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Note: If you use this function to configure the system clock; then there |
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is no need to call the 2 first functions listed above, since SystemCoreClock |
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variable is updated automatically. |
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*/ |
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uint32_t SystemCoreClock = 2000000U; |
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const uint8_t AHBPrescTable[16] = {0U, 0U, 0U, 0U, 0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U, 6U, 7U, 8U, 9U}; |
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const uint8_t APBPrescTable[8] = {0U, 0U, 0U, 0U, 1U, 2U, 3U, 4U}; |
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const uint8_t PLLMulTable[9] = {3U, 4U, 6U, 8U, 12U, 16U, 24U, 32U, 48U}; |
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/** |
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* @} |
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*/ |
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/** @addtogroup STM32L0xx_System_Private_FunctionPrototypes |
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* @{ |
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*/ |
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/** |
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* @} |
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*/ |
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/** @addtogroup STM32L0xx_System_Private_Functions |
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* @{ |
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*/ |
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/** |
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* @brief Setup the microcontroller system. |
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* @param None |
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* @retval None |
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*/ |
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void SystemInit (void) |
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{ |
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/*!< Set MSION bit */ |
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RCC->CR |= (uint32_t)0x00000100U; |
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/*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ |
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RCC->CFGR &= (uint32_t) 0x88FF400CU; |
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/*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */ |
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RCC->CR &= (uint32_t)0xFEF6FFF6U; |
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/*!< Reset HSI48ON bit */ |
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RCC->CRRCR &= (uint32_t)0xFFFFFFFEU; |
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/*!< Reset HSEBYP bit */ |
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RCC->CR &= (uint32_t)0xFFFBFFFFU; |
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/*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */ |
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RCC->CFGR &= (uint32_t)0xFF02FFFFU; |
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/*!< Disable all interrupts */ |
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RCC->CIER = 0x00000000U; |
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/* Configure the Vector Table location add offset address ------------------*/ |
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#ifdef VECT_TAB_SRAM |
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SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ |
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#else |
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SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ |
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#endif |
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} |
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/** |
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* @brief Update SystemCoreClock according to Clock Register Values |
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* The SystemCoreClock variable contains the core clock (HCLK), it can |
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* be used by the user application to setup the SysTick timer or configure |
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* other parameters. |
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* |
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* @note Each time the core clock (HCLK) changes, this function must be called |
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* to update SystemCoreClock variable value. Otherwise, any configuration |
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* based on this variable will be incorrect. |
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* |
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* @note - The system frequency computed by this function is not the real |
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* frequency in the chip. It is calculated based on the predefined |
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* constant and the selected clock source: |
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* |
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* - If SYSCLK source is MSI, SystemCoreClock will contain the MSI |
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* value as defined by the MSI range. |
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* |
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* - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) |
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* |
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* - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) |
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* |
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* - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) |
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* or HSI_VALUE(*) multiplied/divided by the PLL factors. |
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* |
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* (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value |
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* 16 MHz) but the real value may vary depending on the variations |
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* in voltage and temperature. |
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* |
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* (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value |
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* 8 MHz), user has to ensure that HSE_VALUE is same as the real |
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* frequency of the crystal used. Otherwise, this function may |
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* have wrong result. |
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* |
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* - The result of this function could be not correct when using fractional |
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* value for HSE crystal. |
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* @param None |
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* @retval None |
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*/ |
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void SystemCoreClockUpdate (void) |
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{ |
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uint32_t tmp = 0U, pllmul = 0U, plldiv = 0U, pllsource = 0U, msirange = 0U; |
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uint32_t hsi_value; |
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/* added by olikraus@gmail.com: The HSIDIV flag was not considered in the original code */ |
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hsi_value = 16000000UL; |
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if ( (RCC->CR & RCC_CR_HSIDIVF) != 0 ) |
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hsi_value /= 4; |
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/* Get SYSCLK source -------------------------------------------------------*/ |
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tmp = RCC->CFGR & RCC_CFGR_SWS; |
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switch (tmp) |
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{ |
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case 0x04U: /* HSI used as system clock */ |
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SystemCoreClock = hsi_value; |
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break; |
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case 0x08U: /* HSE used as system clock */ |
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SystemCoreClock = HSE_VALUE; |
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break; |
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case 0x0CU: /* PLL used as system clock */ |
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/* Get PLL clock source and multiplication factor ----------------------*/ |
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pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; |
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plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; |
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pllmul = PLLMulTable[(pllmul >> 18U)]; |
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plldiv = (plldiv >> 22U) + 1U; |
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pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; |
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if (pllsource == 0x00U) |
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{ |
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/* HSI oscillator clock selected as PLL clock entry */ |
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SystemCoreClock = (((hsi_value) * pllmul) / plldiv); |
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} |
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else |
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{ |
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/* HSE selected as PLL clock entry */ |
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SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); |
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} |
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break; |
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case 0x00U: /* MSI used as system clock */ |
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default: /* MSI used as system clock */ |
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msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13U; |
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SystemCoreClock = (32768U * (1U << (msirange + 1U))); |
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break; |
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} |
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/* Compute HCLK clock frequency --------------------------------------------*/ |
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/* Get HCLK prescaler */ |
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tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4U)]; |
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/* HCLK clock frequency */ |
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SystemCoreClock >>= tmp; |
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} |
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/** |
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* @} |
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*/ |
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/** |
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* @} |
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*/ |
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/** |
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* @} |
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*/ |
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/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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