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391 lines
11 KiB
391 lines
11 KiB
/* |
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adc_tim_test |
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Example for the STM32L031 Eval Board with 128x64 OLED at PA13/PA14 |
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LED: PA1 / AF2: TIM2_CH2 |
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VarRes: PA5 / ADC CH5 |
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*/ |
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#include <stdio.h> |
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#include "stm32l031xx.h" |
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#include "delay.h" |
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#include "u8x8.h" |
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/*=======================================================================*/ |
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/* external functions */ |
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uint8_t u8x8_gpio_and_delay_stm32l0(u8x8_t *u8x8, uint8_t msg, uint8_t arg_int, void *arg_ptr); |
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/*=======================================================================*/ |
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/* global variables */ |
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u8x8_t u8x8; // u8x8 object |
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uint8_t u8x8_x, u8x8_y; // current position on the screen |
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volatile unsigned long SysTickCount = 0; |
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/*=======================================================================*/ |
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void __attribute__ ((interrupt, used)) SysTick_Handler(void) |
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{ |
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SysTickCount++; |
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} |
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void setHSIClock() |
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{ |
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/* test if the current clock source is something else than HSI */ |
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if ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) |
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{ |
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/* enable HSI */ |
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RCC->CR |= RCC_CR_HSION; |
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/* wait until HSI becomes ready */ |
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while ( (RCC->CR & RCC_CR_HSIRDY) == 0 ) |
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; |
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/* enable the HSI "divide by 4" bit */ |
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RCC->CR |= (uint32_t)(RCC_CR_HSIDIVEN); |
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/* wait until the "divide by 4" flag is enabled */ |
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while((RCC->CR & RCC_CR_HSIDIVF) == 0) |
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; |
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/* then use the HSI clock */ |
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RCC->CFGR = (RCC->CFGR & (uint32_t) (~RCC_CFGR_SW)) | RCC_CFGR_SW_HSI; |
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/* wait until HSI clock is used */ |
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) |
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; |
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} |
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/* disable PLL */ |
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RCC->CR &= (uint32_t)(~RCC_CR_PLLON); |
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/* wait until PLL is inactive */ |
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while((RCC->CR & RCC_CR_PLLRDY) != 0) |
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; |
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/* set latency to 1 wait state */ |
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FLASH->ACR |= FLASH_ACR_LATENCY; |
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/* At this point the HSI runs with 4 MHz */ |
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/* Multiply by 16 device by 2 --> 32 MHz */ |
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RCC->CFGR = (RCC->CFGR & (~(RCC_CFGR_PLLMUL| RCC_CFGR_PLLDIV ))) | (RCC_CFGR_PLLMUL16 | RCC_CFGR_PLLDIV2); |
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/* enable PLL */ |
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RCC->CR |= RCC_CR_PLLON; |
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/* wait until the PLL is ready */ |
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while ((RCC->CR & RCC_CR_PLLRDY) == 0) |
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; |
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/* use the PLL has clock source */ |
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RCC->CFGR |= (uint32_t) (RCC_CFGR_SW_PLL); |
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/* wait until the PLL source is active */ |
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) |
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; |
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SystemCoreClockUpdate(); /* Update SystemCoreClock global variable */ |
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} |
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/* |
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Enable several power regions: PWR, GPIOA |
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This must be executed after each reset. |
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*/ |
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void startUp(void) |
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{ |
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RCC->IOPENR |= RCC_IOPENR_IOPAEN; /* Enable clock for GPIO Port A */ |
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RCC->APB1ENR |= RCC_APB1ENR_PWREN; /* enable power interface (PWR) */ |
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PWR->CR |= PWR_CR_DBP; /* activate write access to RCC->CSR and RTC */ |
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SysTick->LOAD = (SystemCoreClock/1000)*50 - 1; /* 50ms task */ |
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SysTick->VAL = 0; |
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SysTick->CTRL = 7; /* enable, generate interrupt (SysTick_Handler), do not divide by 2 */ |
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} |
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/*=======================================================================*/ |
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/* u8x8 display procedures */ |
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void initDisplay(void) |
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{ |
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u8x8_Setup(&u8x8, u8x8_d_ssd1306_128x64_noname, u8x8_cad_ssd13xx_i2c, u8x8_byte_sw_i2c, u8x8_gpio_and_delay_stm32l0); |
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u8x8_InitDisplay(&u8x8); |
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u8x8_ClearDisplay(&u8x8); |
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u8x8_SetPowerSave(&u8x8, 0); |
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u8x8_SetFont(&u8x8, u8x8_font_amstrad_cpc_extended_r); |
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u8x8_x = 0; |
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u8x8_y = 0; |
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} |
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void outChar(uint8_t c) |
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{ |
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if ( u8x8_x >= u8x8_GetCols(&u8x8) ) |
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{ |
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u8x8_x = 0; |
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u8x8_y++; |
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} |
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u8x8_DrawGlyph(&u8x8, u8x8_x, u8x8_y, c); |
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u8x8_x++; |
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} |
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void outStr(const char *s) |
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{ |
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while( *s ) |
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outChar(*s++); |
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} |
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void outHexHalfByte(uint8_t b) |
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{ |
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b &= 0x0f; |
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if ( b < 10 ) |
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outChar(b+'0'); |
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else |
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outChar(b+'a'-10); |
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} |
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void outHex8(uint8_t b) |
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{ |
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outHexHalfByte(b >> 4); |
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outHexHalfByte(b); |
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} |
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void outHex16(uint16_t v) |
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{ |
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outHex8(v>>8); |
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outHex8(v); |
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} |
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void outHex32(uint32_t v) |
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{ |
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outHex16(v>>16); |
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outHex16(v); |
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} |
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void setRow(uint8_t r) |
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{ |
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u8x8_x = 0; |
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u8x8_y = r; |
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} |
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/*=======================================================================*/ |
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void initADC(void) |
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{ |
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//__disable_irq(); |
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/* ADC Clock Enable */ |
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RCC->APB2ENR |= RCC_APB2ENR_ADCEN; /* enable ADC clock */ |
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__NOP(); /* let us wait for some time */ |
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__NOP(); /* let us wait for some time */ |
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/* ADC Reset */ |
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RCC->APB2RSTR |= RCC_APB2RSTR_ADCRST; |
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__NOP(); /* let us wait for some time */ |
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__NOP(); /* let us wait for some time */ |
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RCC->APB2RSTR &= ~RCC_APB2RSTR_ADCRST; |
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__NOP(); /* let us wait for some time */ |
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__NOP(); /* let us wait for some time */ |
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/* ADC Basic Setup */ |
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ADC1->IER = 0; /* do not allow any interrupts */ |
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ADC1->CFGR2 &= ~ADC_CFGR2_CKMODE; /* select HSI16 clock */ |
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ADC1->CR |= ADC_CR_ADVREGEN; /* enable ADC voltage regulator, probably not required, because this is automatically activated */ |
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ADC->CCR |= ADC_CCR_VREFEN; /* Wake-up the VREFINT */ |
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ADC->CCR |= ADC_CCR_TSEN; /* Wake-up the temperature sensor */ |
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__NOP(); /* let us wait for some time */ |
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__NOP(); /* let us wait for some time */ |
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/* CALIBRATION */ |
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if ((ADC1->CR & ADC_CR_ADEN) != 0) /* clear ADEN flag if required */ |
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{ |
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/* is this correct, i think we must use the disable flag here */ |
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ADC1->CR &= (uint32_t)(~ADC_CR_ADEN); |
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} |
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ADC1->CR |= ADC_CR_ADCAL; /* start calibration */ |
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while ((ADC1->ISR & ADC_ISR_EOCAL) == 0) /* wait for clibration finished */ |
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{ |
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} |
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ADC1->ISR |= ADC_ISR_EOCAL; /* clear the status flag, by writing 1 to it */ |
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__NOP(); /* not sure why, but some nop's are required here, at least 4 of them */ |
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__NOP(); |
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__NOP(); |
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__NOP(); |
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__NOP(); |
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__NOP(); |
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/* ENABLE ADC */ |
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ADC1->ISR |= ADC_ISR_ADRDY; /* clear ready flag */ |
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ADC1->CR |= ADC_CR_ADEN; /* enable ADC */ |
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while ((ADC1->ISR & ADC_ISR_ADRDY) == 0) /* wait for ADC */ |
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{ |
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} |
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} |
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/* |
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ch0 PA0 pin 6 |
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ch1 PA1 pin 7 |
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ch2 PA2 pin 8 |
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ch3 PA3 pin 9 |
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ch4 PA4 pin 10 |
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ch5 PA5 pin 11 |
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ch6 PA6 pin 12 |
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ch7 PA7 pin 13 |
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ch8 PB0 - |
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ch9 PB1 pin 14 |
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ch 0..15: GPIO |
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ch 16: ??? |
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ch 17: vref (bandgap) |
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ch18: temperature sensor |
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returns 12 bit result, right aligned |
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*/ |
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uint16_t getADC(uint8_t ch) |
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{ |
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uint32_t data; |
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uint32_t i; |
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/* CONFIGURE ADC */ |
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ADC1->CFGR1 &= ~ADC_CFGR1_EXTEN; /* software enabled conversion start */ |
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ADC1->CFGR1 &= ~ADC_CFGR1_ALIGN; /* right alignment */ |
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ADC1->CFGR1 &= ~ADC_CFGR1_RES; /* 12 bit resolution */ |
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ADC1->CHSELR = 1<<ch; /* Select channel */ |
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ADC1->SMPR |= ADC_SMPR_SMP_0 | ADC_SMPR_SMP_1 | ADC_SMPR_SMP_2; /* Select a sampling mode of 111 (very slow)*/ |
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/* DO CONVERSION */ |
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data = 0; |
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for( i = 0; i < 8; i++ ) |
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{ |
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ADC1->CR |= ADC_CR_ADSTART; /* start the ADC conversion */ |
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while ((ADC1->ISR & ADC_ISR_EOC) == 0) /* wait end of conversion */ |
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{ |
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} |
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data += ADC1->DR; /* get ADC result and clear the ISR_EOC flag */ |
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} |
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data >>= 3; |
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return data; |
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} |
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/*=======================================================================*/ |
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void initTIM(void) |
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{ |
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/* enable clock for TIM2 */ |
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RCC->APB1ENR |= RCC_APB1ENR_TIM2EN; |
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/*enable clock for GPIOA */ |
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RCC->IOPENR |= RCC_IOPENR_IOPAEN; /* Enable clock for GPIO Port A */ |
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__NOP(); /* extra delay for clock stabilization required? */ |
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__NOP(); |
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/* prescalar for AHB and APB1 */ |
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/* reselt defaults for HPRE and PPRE1: no clock division */ |
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// RCC->CFGR &= ~RCC_CFGR_HPRE; |
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// RCC->CFGR |= RCC_CFGR_HPRE_DIV1; |
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// RCC->CFGR &= ~RCC_CFGR_PPRE1; |
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// RCC->CFGR |= RCC_CFGR_PPRE1_DIV1; |
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/* configure GPIOA PA1 for TIM2 */ |
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GPIOA->MODER &= ~GPIO_MODER_MODE1; /* clear mode for PA9 */ |
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GPIOA->MODER |= GPIO_MODER_MODE1_1; /* alt fn */ |
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GPIOA->OTYPER &= ~GPIO_OTYPER_OT_1; /* push-pull */ |
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GPIOA->AFR[0] &= ~(15<<4); /* Clear Alternate Function PA1 */ |
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GPIOA->AFR[0] |= 2<<4; /* AF2 Alternate Function PA1 */ |
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/* TIM2 configure */ |
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/* disable all interrupts */ |
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//TIM2->DIER = 0; /* 0 is reset default value */ |
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/* clear everything, including the "Update disable" flag, so that updates */ |
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/* are generated */ |
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// TIM2->CR1 = 0; /* 0 is reset default value */ |
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//TIM2->CR1 |= TIM_CR1_ARPE; // ARR is not modified so constant update is ok |
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/* Update request by manual UG bit setting or slave controller */ |
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/* both is not required here */ |
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/* so, update request by couter over/underflow remains */ |
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//TIM2->CR1 |= TIM_CR1_URS; /* only udf/ovf generae events */ |
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TIM2->ARR = 4096; /* total cycle count */ |
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TIM2->CCR2 = 1024; /* duty cycle */ |
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//TIM2->CCMR1 &= ~TIM_CCMR1_OC2CE; /* disable clear output compare 2 **/ |
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TIM2->CCMR1 |= TIM_CCMR1_OC2M; /* all 3 bits set: PWM Mode 2 */ |
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//TIM2->CCMR1 &= ~TIM_CCMR1_OC1M_0; /* 110: PWM Mode 1 */ |
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TIM2->CCMR1 |= TIM_CCMR1_OC2PE; /* preload enable CCR2 is preloaded*/ |
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// TIM2->CCMR1 &= ~TIM_CCMR1_OC2FE; /* fast disable (reset default) */ |
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// TIM2->CCMR1 &= ~TIM_CCMR1_CC2S; /* configure cc2 as output (this is reset default) */ |
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//TIM2->EGR |= TIM_EGR_CC2G; /* capture event cc2 */ |
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TIM2->CCER |= TIM_CCER_CC2E; /* set output enable */ |
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//TIM2->CCER |= TIM_CCER_CC2P; /* polarity 0: normal (reset default) / 1: inverted*/ |
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TIM2->PSC = 7; |
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TIM2->CR1 |= TIM_CR1_CEN; /* counter enable */ |
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} |
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/*=======================================================================*/ |
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void main() |
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{ |
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uint16_t adc_value; |
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uint16_t i; |
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setHSIClock(); /* enable 32 MHz Clock */ |
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startUp(); /* enable systick irq and several power regions */ |
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initDisplay(); /* aktivate display */ |
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initADC(); |
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RCC->IOPENR |= RCC_IOPENR_IOPAEN; /* Enable clock for GPIO Port A */ |
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__NOP(); |
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__NOP(); |
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GPIOA->MODER &= ~GPIO_MODER_MODE1; /* clear mode for PA1 */ |
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GPIOA->MODER |= GPIO_MODER_MODE1_0; /* Output mode for PA1 */ |
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GPIOA->OTYPER &= ~GPIO_OTYPER_OT_1; /* no Push/Pull for PA1 */ |
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GPIOA->OSPEEDR &= ~GPIO_OSPEEDER_OSPEED1; /* low speed for PA1 */ |
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GPIOA->PUPDR &= ~GPIO_PUPDR_PUPD1; /* no pullup/pulldown for PA1 */ |
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GPIOA->BSRR = GPIO_BSRR_BS_1; /* atomic set PA1 */ |
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initTIM(); |
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setRow(0); outStr("ADC Test"); |
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setRow(2); outStr("ch5 pin11: "); |
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setRow(3); outHex16(getADC(5)); |
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setRow(4); outStr("bandgap: "); |
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setRow(5); outHex16(getADC(17)); |
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setRow(6); outStr("temp: "); |
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setRow(7); outHex16(getADC(18)); |
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for(;;) |
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{ |
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adc_value = getADC(5); |
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TIM2->CCR2 = adc_value; |
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setRow(3); outHex16(adc_value); |
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} |
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}
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