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220 lines
6.2 KiB
220 lines
6.2 KiB
6 years ago
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/*
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boost converter project for the STM32L011x4
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STM32L011D3P D=14Pin 3=8KB P=TTSOP
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STM32L011D4P D=14Pin 4=16KB P=TTSOP
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STM32L011F3P F=20Pin 3=8KB P=TTSOP
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STM32L011F4P F=20Pin 4=16KB P=TTSOP
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TSSOP20:
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PB9/BOOT 1 20 PA14
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PC14 2 19 PA13
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PC15 3 18 PA10 TIM21_CH1, TIM2_CH3
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Reset 4 17 PA9 TIM21_CH2
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VDDA 5 16 VDD
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PA0 C1- 6 15 GND
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PA1 C1+ 7 14 PB1 ADC9
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PA2 C2- TX 8 13 PA7 C2+
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PA3 C2+ RX 9 12 PA6 ADC6
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PA4 C1- C2- 10 11 PA5 C1- C2-
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Comp 2:
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Input: REFINT /4
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Input: PA7 (C2+),
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Output: PA9 (TIM21_CH2)
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Comp 1:
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Input: REFINT
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Input: PA1 (C1+)
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Output: PA10 (TIM2_CH3)
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*/
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#include "stm32l011xx.h"
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/*===============================================*/
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/*
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systick IRQ
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*/
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volatile unsigned long SysTickCount = 0;
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void __attribute__ ((interrupt, used)) SysTick_Handler(void)
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{
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SysTickCount++;
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if ( SysTickCount & 1 )
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GPIOA->BSRR = GPIO_BSRR_BS_0; /* atomic set PA0 */
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else
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GPIOA->BSRR = GPIO_BSRR_BR_0; /* atomic clr PA0 */
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/*
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if ( COMP2->CSR & COMP_CSR_COMP2VALUE )
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GPIOA->BSRR = GPIO_BSRR_BS_0;
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else
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GPIOA->BSRR = GPIO_BSRR_BR_0;
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*/
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}
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/*===============================================*/
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/*
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boost converter
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PA6=Output to N-MOS Gate
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PA7=Reference Input
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*/
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void boost_converter(void)
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{
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/* assumes, that SYSCFG_CRGR3 is not locked */
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/* assumes, that COMP2 is not locked */
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/* setup internal reference (ca. 1.2V) */
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SYSCFG->CFGR3 |= SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP; /* enable VREFINT during low power mode */
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while( (SYSCFG->CFGR3 & SYSCFG_CFGR3_VREFINT_RDYF) == 0 ) /* wait for VREFINT until it becomes ready */
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;
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/* configure PA7 as COMP2 Plus input */
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/* GPIO has to be in input state without any pull up/down resistor: This is default, so nothing needs to be done here */
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/* configure PA9 as TIM21 output */
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GPIOA->AFR[1] &= ~GPIO_AFRH_AFRH1_Msk;
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GPIOA->AFR[1] |= 5<<GPIO_AFRH_AFRH1_Pos; /* AF5 selects TIM21 */
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GPIOA->MODER &= ~GPIO_MODER_MODE9; /* clear mode */
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GPIOA->MODER |= GPIO_MODER_MODE9_1; /* Alternate Function Mode */
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GPIOA->OTYPER &= ~GPIO_OTYPER_OT_9; /* no Push/Pull */
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GPIOA->OSPEEDR &= ~GPIO_OSPEEDER_OSPEED9; /* low speed */
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GPIOA->PUPDR &= ~GPIO_PUPDR_PUPD9; /* no pullup/pulldown */
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GPIOA->BSRR = GPIO_BSRR_BR_9; /* atomic clr */
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/* setup COMP2 */
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/*
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COMP2 has only one register: CSR
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Bit 31: Lock bit, will lock CSR until next reset if set to 1
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Bit 30: Output value, considering polarity
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Bit 15: Polarity, 0: Not inverted
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Bits 10:8: Plus input
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000: PA3
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001: PB4
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010: PB5
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011: PB6
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100: PB7
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101: PA7 (for category 1 devices only)
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Bits 6:4: Minus input
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000: VREFINT
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001: PA2
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010: PA4
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011: PA5
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100: 1/4 VREFINT
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101: 1/2 VREFINT
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110: 3/4 VREFINT
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111: PB
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Bit 3: Speed selection, 0: Low speed
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Bit 0: Enable
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*/
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/* select PA7 as positive input --> 101, only available for the STM32L011 */
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COMP2->CSR &= ~(uint32_t)COMP_CSR_COMP2INPSEL;
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COMP2->CSR |= COMP_CSR_COMP2INPSEL_0 | COMP_CSR_COMP2INPSEL_2;
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/*
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0.306V
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20mA 15 Ohm 20.4mA
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20mA 18 Ohm 17mA
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350mA 1 Ohm 306mA --> 300mWatt
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*/
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/* select 1/4 internal reference voltage --> 0.306 Volt -->100 */
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COMP2->CSR &= ~(uint32_t)COMP_CSR_COMP2INNSEL;
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COMP2->CSR |= COMP_CSR_COMP2INNSEL_2;
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/* invert polarity */
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//COMP2->CSR |= COMP_CSR_COMP2POLARITY;
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/* comparator enable */
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COMP2->CSR |= COMP_CSR_COMP2EN;
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/* setup PWM mode for TIM21 */
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/* configure output compare for channel 2 of TIM21 */
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TIM21->CCMR1 &= ~(uint32_t)TIM_CCMR1_CC2S;
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/* configure pwm mode 1 */
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TIM21->CCMR1 &= ~(uint32_t)TIM_CCMR1_OC2M; /* clear mode to 000 */
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TIM21->CCMR1 |= TIM_CCMR1_OC2M_2 | TIM_CCMR1_OC2M_1; /* pwm mode 1 (110) */
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TIM21->CCMR1 |= TIM_CCMR1_OC2PE; /* load modified CCR1 during update event only */
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TIM21->PSC = 0; /* run with max speed (2 MHz after reset) */
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TIM21->ARR = 20; /* period of 20 clocks (100KHz if sys clock is not modified) */
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TIM21->CCR2 = 5; /* a value between 0 and ARR, which defines the duty cycle */
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/* output the result of channel 2 to PA9 */
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TIM21->CCER |= TIM_CCER_CC2E;
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/* do not invert the output polarity (this is also the default value) */
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TIM21->CCER &= ~(uint32_t)TIM_CCER_CC2P;
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/* use up counter (this is also the default value) */
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TIM21->CR1 &= ~(uint32_t)TIM_CR1_DIR;
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/* do not use "one pulse mode" (continues mode, this is also the default value) */
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TIM21->CR1 &= ~(uint32_t)TIM_CR1_OPM;
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/* always generate an update event (this is also default) */
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TIM21->CR1 &= ~(uint32_t)TIM_CR1_UDIS;
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/* update event can be caused by UG bit and overflow (this is default) */
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TIM21->CR1 &= ~(uint32_t)TIM_CR1_URS;
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/* connect COMP2 with TIM21 */
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/* the following two bits are not documented in RM0377 */
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/* However, it is mentioned in "A.9.10 ETR configuration to clear OCxREF code example" */
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TIM21->CCMR1 |= TIM_CCMR1_OC2CE; /* enable clearing on OC1 for ETR clearing */
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TIM21->SMCR |= TIM_SMCR_OCCS; /* Select ETR as OCREF clear source (reserved bit = 1) */
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//TIM21->EGR |= TIM_EGR_UG;
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TIM21->OR &= ~TIM21_OR_ETR_RMP_Msk;
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TIM21->OR |= TIM21_OR_ETR_RMP_0; /* bit pattern 01: connect with COMP2 */
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/* enable the counter */
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TIM21->CR1 |= TIM_CR1_CEN;
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}
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int main()
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{
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RCC->IOPENR |= RCC_IOPENR_IOPAEN; /* Enable clock for GPIO Port A */
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RCC->APB2ENR |= RCC_APB2ENR_ADCEN;
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RCC->APB2ENR |= RCC_APB2ENR_TIM21EN;
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RCC->APB2ENR |= RCC_APB2ENR_SYSCFGEN;
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RCC->APB1ENR |= RCC_APB1ENR_TIM2EN;
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__NOP();
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__NOP();
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GPIOA->MODER &= ~GPIO_MODER_MODE0; /* clear mode for PA0 */
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GPIOA->MODER |= GPIO_MODER_MODE0_0; /* Output mode for PA0 */
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GPIOA->OTYPER &= ~GPIO_OTYPER_OT_0; /* no Push/Pull for PA0 */
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GPIOA->OSPEEDR &= ~GPIO_OSPEEDER_OSPEED0; /* low speed for PA0 */
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GPIOA->PUPDR &= ~GPIO_PUPDR_PUPD0; /* no pullup/pulldown for PA0 */
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GPIOA->BSRR = GPIO_BSRR_BR_0; /* atomic clr PA0 */
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boost_converter();
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SysTick->LOAD = 2000*500 - 1;
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SysTick->VAL = 0;
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SysTick->CTRL = 7; /* enable, generate interrupt (SysTick_Handler), do not divide by 2 */
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for(;;)
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;
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}
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