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159 lines
4.4 KiB
159 lines
4.4 KiB
/* LED blink project for the STM32L031 */ |
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#include "stm32l031xx.h" |
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#include "display.h" |
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#include "delay.h" |
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/*=======================================================================*/ |
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/* global variables */ |
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volatile unsigned long SysTickCount = 0; |
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/*=======================================================================*/ |
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void __attribute__ ((interrupt, used)) SysTick_Handler(void) |
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{ |
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SysTickCount++; |
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} |
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void setHSIClock() |
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{ |
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/* test if the current clock source is something else than HSI */ |
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if ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) |
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{ |
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/* enable HSI */ |
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RCC->CR |= RCC_CR_HSION; |
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/* wait until HSI becomes ready */ |
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while ( (RCC->CR & RCC_CR_HSIRDY) == 0 ) |
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; |
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/* enable the HSI "divide by 4" bit */ |
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RCC->CR |= (uint32_t)(RCC_CR_HSIDIVEN); |
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/* wait until the "divide by 4" flag is enabled */ |
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while((RCC->CR & RCC_CR_HSIDIVF) == 0) |
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; |
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/* then use the HSI clock */ |
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RCC->CFGR = (RCC->CFGR & (uint32_t) (~RCC_CFGR_SW)) | RCC_CFGR_SW_HSI; |
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/* wait until HSI clock is used */ |
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_HSI) |
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; |
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} |
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/* disable PLL */ |
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RCC->CR &= (uint32_t)(~RCC_CR_PLLON); |
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/* wait until PLL is inactive */ |
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while((RCC->CR & RCC_CR_PLLRDY) != 0) |
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; |
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/* set latency to 1 wait state */ |
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FLASH->ACR |= FLASH_ACR_LATENCY; |
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/* At this point the HSI runs with 4 MHz */ |
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/* Multiply by 16 device by 2 --> 32 MHz */ |
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RCC->CFGR = (RCC->CFGR & (~(RCC_CFGR_PLLMUL| RCC_CFGR_PLLDIV ))) | (RCC_CFGR_PLLMUL16 | RCC_CFGR_PLLDIV2); |
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/* enable PLL */ |
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RCC->CR |= RCC_CR_PLLON; |
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/* wait until the PLL is ready */ |
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while ((RCC->CR & RCC_CR_PLLRDY) == 0) |
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; |
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/* use the PLL has clock source */ |
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RCC->CFGR |= (uint32_t) (RCC_CFGR_SW_PLL); |
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/* wait until the PLL source is active */ |
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while ((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL) |
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; |
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} |
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int main() |
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{ |
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setHSIClock(); |
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SystemCoreClockUpdate(); /* Update SystemCoreClock() */ |
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//SystemCoreClock = 32000000UL; |
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SysTick->LOAD = (SystemCoreClock/1000)*50 - 1; /* 50ms task */ |
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SysTick->VAL = 0; |
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SysTick->CTRL = 7; /* enable, generate interrupt (SysTick_Handler), do not divide by 2 */ |
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RCC->IOPENR |= RCC_IOPENR_IOPAEN; /* Enable clock for GPIO Port A */ |
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__NOP(); |
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__NOP(); |
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GPIOA->MODER &= ~GPIO_MODER_MODE13; /* clear mode for PA13 */ |
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GPIOA->MODER |= GPIO_MODER_MODE13_0; /* Output mode for PA13 */ |
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GPIOA->OTYPER &= ~GPIO_OTYPER_OT_13; /* Push/Pull for PA13 */ |
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GPIOA->OSPEEDR &= ~GPIO_OSPEEDER_OSPEED13; /* low speed for PA13 */ |
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GPIOA->PUPDR &= ~GPIO_PUPDR_PUPD13; /* no pullup/pulldown for PA13 */ |
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GPIOA->BSRR = GPIO_BSRR_BR_13; /* atomic clr PA13 */ |
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GPIOA->BSRR = GPIO_BSRR_BS_13; /* atomic set PA13 */ |
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display_Init(); |
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display_Write("STM32L031\n"); |
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display_WriteUnsigned(SystemCoreClock); |
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display_Write(" Hz\n"); |
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/* real time clock enable */ |
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RCC->APB1ENR |= RCC_APB1ENR_PWREN; /* enable power interface */ |
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PWR->CR |= PWR_CR_DBP; /* activate write access to RCC->CSR */ |
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/* externel 32K clock source */ |
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RCC->CSR |= RCC_CSR_LSEBYP; /* bypass oscillator */ |
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/* externel 32K oscillator */ |
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//RCC->CSR &= ~RCC_CSR_LSEBYP; /* no bypass oscillator */ |
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//RCC->CSR &= ~RCC_CSR_LSEDRV_Msk /* lowest drive */ |
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//RCC->CSR |= RCC_CSR_LSEDRV_0; /* medium low drive */ |
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RCC->CSR |= RCC_CSR_LSEON; /* enable low speed external clock */ |
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delay_micro_seconds(100000*5); /* LSE requires between 100ms to 200ms */ |
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if ( RCC->CSR & RCC_CSR_LSERDY ) |
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display_Write("32K Clock Ready\n"); |
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else |
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display_Write("32K Clock Error\n"); |
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RCC->CSR &= ~RCC_CSR_RTCSEL_Msk; /* no clock selection for RTC */ |
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RCC->CSR |= RCC_CSR_RTCSEL_LSE; /* select LSE */ |
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RCC->CSR |= RCC_CSR_RTCEN; /* enable RTC */ |
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RTC->WPR = 0x0ca; /* disable RTC write protection */ |
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RTC->WPR = 0x053; |
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RTC->ISR = RTC_ISR_INIT; /* request RTC stop */ |
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while((RTC->ISR & RTC_ISR_INITF)!=RTC_ISR_INITF) /* wait for stop */ |
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; |
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RTC->PRER = 0x07f00ff; |
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RTC->TR = 0; |
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RTC->ISR =~ RTC_ISR_INIT; /* start RTC */ |
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RTC->WPR = 0; /* enable RTC write protection */ |
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RTC->WPR = 0; |
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//PWR->CR &= ~PWR_CR_DBP; /* disable write access to RCC->CSR */ |
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for(;;) |
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{ |
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delay_micro_seconds(500000); |
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GPIOA->BSRR = GPIO_BSRR_BS_13; /* atomic set PA13 */ |
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delay_micro_seconds(500000); |
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GPIOA->BSRR = GPIO_BSRR_BR_13; /* atomic clr PA13 */ |
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display_WriteUnsigned(RTC->TR); |
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display_Write("\n"); |
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} |
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}
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