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@ -137,10 +137,17 @@ void sx127x_isr(void *arg) {
@@ -137,10 +137,17 @@ void sx127x_isr(void *arg) {
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} |
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} |
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#define _TX_CHECK(_ret) \ |
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ret = (_ret); \ |
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if (ret != ESP_OK) { \ |
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goto error; \ |
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} |
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void sx127x_do_tx(sx127x_t *handle, sx127x_packet_t *packet) { |
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uint8_t op_mode, irq_flags, config_2; |
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esp_err_t ret; |
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uint8_t op_mode, irq_flags, config_2; |
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while (handle->task_state == SX127X_TASK_RUNNING) { |
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sx127x_read_register(handle, REG_OP_MODE, &op_mode); |
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_TX_CHECK(sx127x_read_register(handle, REG_OP_MODE, &op_mode)); |
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uint8_t mode = op_mode & SX127X_MODE; |
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if (mode != SX127X_MODE_TX && mode != SX127X_MODE_FS_TX) { |
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break; |
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@ -148,39 +155,44 @@ void sx127x_do_tx(sx127x_t *handle, sx127x_packet_t *packet) {
@@ -148,39 +155,44 @@ void sx127x_do_tx(sx127x_t *handle, sx127x_packet_t *packet) {
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vTaskDelay(1); // wait for finish transmitting
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} |
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sx127x_standby(handle); |
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_TX_CHECK(sx127x_standby(handle)); |
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sx127x_read_register(handle, REG_IRQ_FLAGS, &irq_flags); |
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_TX_CHECK(sx127x_read_register(handle, REG_IRQ_FLAGS, &irq_flags)); |
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if (irq_flags & IRQ_TX_DONE_MASK) { |
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// clear tx done bit
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sx127x_write_register(handle, REG_IRQ_FLAGS, IRQ_TX_DONE_MASK); |
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_TX_CHECK(sx127x_write_register(handle, REG_IRQ_FLAGS, IRQ_TX_DONE_MASK)); |
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} |
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sx127x_read_register(handle, REG_MODEM_CONFIG_2, &config_2); |
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_TX_CHECK(sx127x_read_register(handle, REG_MODEM_CONFIG_2, &config_2)); |
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config_2 &= ~0x01; // set explicit header mode TODO: implicit header?
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sx127x_write_register(handle, REG_MODEM_CONFIG_2, config_2); |
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_TX_CHECK(sx127x_write_register(handle, REG_MODEM_CONFIG_2, config_2)); |
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sx127x_write_register(handle, REG_FIFO_ADDR_PTR, 0); |
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sx127x_write_register(handle, REG_PAYLOAD_LENGTH, 0); |
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_TX_CHECK(sx127x_write_register(handle, REG_FIFO_ADDR_PTR, 0)); |
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_TX_CHECK(sx127x_write_register(handle, REG_PAYLOAD_LENGTH, 0)); |
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sx127x_write_fifo(handle, packet->data, packet->data_len); |
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sx127x_write_register(handle, REG_PAYLOAD_LENGTH, packet->data_len); |
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_TX_CHECK(sx127x_write_fifo(handle, packet->data, packet->data_len)); |
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_TX_CHECK(sx127x_write_register(handle, REG_PAYLOAD_LENGTH, packet->data_len)); |
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sx127x_write_register(handle, REG_OP_MODE, SX127X_LONG_RANGE | SX127X_MODE_FS_TX); |
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_TX_CHECK(sx127x_write_register(handle, REG_OP_MODE, SX127X_LONG_RANGE | SX127X_MODE_FS_TX)); |
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vTaskDelay(pdMS_TO_TICKS(1)); |
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sx127x_write_register(handle, REG_OP_MODE, SX127X_LONG_RANGE | SX127X_MODE_TX); |
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_TX_CHECK(sx127x_write_register(handle, REG_OP_MODE, SX127X_LONG_RANGE | SX127X_MODE_TX)); |
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// wait for transmission to finish
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while (true) { |
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sx127x_read_register(handle, REG_IRQ_FLAGS, &irq_flags); |
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_TX_CHECK(sx127x_read_register(handle, REG_IRQ_FLAGS, &irq_flags)); |
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if (irq_flags & IRQ_TX_DONE_MASK) { // if the transmission is done
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break; |
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} |
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vTaskDelay(1); |
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} |
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// clear tx done bit
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sx127x_write_register(handle, REG_IRQ_FLAGS, IRQ_TX_DONE_MASK); |
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_TX_CHECK(sx127x_write_register(handle, REG_IRQ_FLAGS, IRQ_TX_DONE_MASK)); |
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error: |
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if (ret != ESP_OK) { |
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const char *error_name = esp_err_to_name(ret); |
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ESP_LOGE(SX127X_TAG, "tx error: %s (%d)", error_name, ret); |
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} |
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// go back to rx mode
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sx127x_write_register(handle, REG_OP_MODE, SX127X_LONG_RANGE | SX127X_MODE_RX_CONT); |
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} |
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@ -222,7 +234,7 @@ esp_err_t sx127x_start(sx127x_t *handle) {
@@ -222,7 +234,7 @@ esp_err_t sx127x_start(sx127x_t *handle) {
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handle->intr_semaphore = xSemaphoreCreateBinary(); |
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// handle->recv_packet_queue = xQueueCreate(8, 10);
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handle->tx_packet_queue = xQueueCreate(4, sizeof(sx127x_packet_t)); |
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handle->tx_packet_queue = xQueueCreate(8, sizeof(sx127x_packet_t)); |
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handle->task_state = SX127X_TASK_RUNNING; |
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BaseType_t pdRet = |
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