From 93b29e0c3f58dc5e28d72a7acee681aa175088de Mon Sep 17 00:00:00 2001 From: Alex Mikhalev Date: Mon, 31 Dec 2018 13:48:11 -0700 Subject: [PATCH] refactor register names to enum --- components/sx127x_driver/sx127x_driver.c | 70 +++++++++++---------- components/sx127x_driver/sx127x_internal.h | 57 ----------------- components/sx127x_driver/sx127x_registers.c | 63 +++++++++---------- components/sx127x_driver/sx127x_registers.h | 67 +++++++++++++++++++- 4 files changed, 132 insertions(+), 125 deletions(-) diff --git a/components/sx127x_driver/sx127x_driver.c b/components/sx127x_driver/sx127x_driver.c index b471ffc..0f4981c 100644 --- a/components/sx127x_driver/sx127x_driver.c +++ b/components/sx127x_driver/sx127x_driver.c @@ -27,20 +27,21 @@ static esp_err_t sx127x_write_config(sx127x_t *hndl) { ret = sx127x_set_frequency(hndl, config->frequency); SX127X_ERROR_CHECK(ret); - ret = sx127x_write_register(hndl, REG_FIFO_TX_BASE_ADDR, 0); + ret = sx127x_write_register(hndl, SX127X_REG_FIFO_TX_BASE_ADDR, 0); SX127X_ERROR_CHECK(ret); - sx127x_write_register(hndl, REG_FIFO_RX_BASE_ADDR, 0); + sx127x_write_register(hndl, SX127X_REG_FIFO_RX_BASE_ADDR, 0); SX127X_ERROR_CHECK(ret); uint8_t reg_lna; - ret = sx127x_read_register(hndl, REG_LNA, ®_lna); + ret = sx127x_read_register(hndl, SX127X_REG_LNA, ®_lna); SX127X_ERROR_CHECK(ret); reg_lna |= 0x03; // set LNA boost - ret = sx127x_write_register(hndl, REG_LNA, reg_lna); + ret = sx127x_write_register(hndl, SX127X_REG_LNA, reg_lna); SX127X_ERROR_CHECK(ret); // set auto AGC - ret = sx127x_write_register(hndl, REG_MODEM_CONFIG_3, CONFIG3_AUTO_AGC); + ret = + sx127x_write_register(hndl, SX127X_REG_MODEM_CONFIG_3, SX127X_CONFIG3_AUTO_AGC); SX127X_ERROR_CHECK(ret); ret = sx127x_set_tx_power(hndl, config->tx_power, true); @@ -113,7 +114,7 @@ esp_err_t sx127x_init(const sx127x_config_t *config, sx127x_t **handle_ptr) { // read version and check that it is compatible uint8_t version; - ret = sx127x_read_register(hndl, REG_VERSION, &version); + ret = sx127x_read_register(hndl, SX127X_REG_VERSION, &version); SX127X_ERROR_CHECK2(ret, sx127x_read_register); SX127X_CHECK(version == 0x12, "unsupported version %#x", ESP_ERR_INVALID_VERSION, version); @@ -163,7 +164,7 @@ static void sx127x_do_tx(sx127x_t *hndl, sx127x_packet_t *packet) { esp_err_t ret; uint8_t op_mode, irq_flags, config_2; while (atomic_load(&hndl->task_state) == SX127X_TASK_RUNNING) { - _TX_CHECK(sx127x_read_register(hndl, REG_OP_MODE, &op_mode)); + _TX_CHECK(sx127x_read_register(hndl, SX127X_REG_OP_MODE, &op_mode)); uint8_t mode = op_mode & SX127X_MODE; if (mode != SX127X_MODE_TX && mode != SX127X_MODE_FS_TX) { break; @@ -173,38 +174,41 @@ static void sx127x_do_tx(sx127x_t *hndl, sx127x_packet_t *packet) { _TX_CHECK(sx127x_standby(hndl)); - _TX_CHECK(sx127x_read_register(hndl, REG_IRQ_FLAGS, &irq_flags)); - if (irq_flags & IRQ_TX_DONE_MASK) { + _TX_CHECK(sx127x_read_register(hndl, SX127X_REG_IRQ_FLAGS, &irq_flags)); + if (irq_flags & SX127X_IRQ_TX_DONE_MASK) { // clear tx done bit - _TX_CHECK(sx127x_write_register(hndl, REG_IRQ_FLAGS, IRQ_TX_DONE_MASK)); + _TX_CHECK( + sx127x_write_register(hndl, SX127X_REG_IRQ_FLAGS, SX127X_IRQ_TX_DONE_MASK)); } - _TX_CHECK(sx127x_read_register(hndl, REG_MODEM_CONFIG_2, &config_2)); + _TX_CHECK(sx127x_read_register(hndl, SX127X_REG_MODEM_CONFIG_2, &config_2)); config_2 &= ~0x01; // set explicit header mode TODO: implicit header? - _TX_CHECK(sx127x_write_register(hndl, REG_MODEM_CONFIG_2, config_2)); + _TX_CHECK(sx127x_write_register(hndl, SX127X_REG_MODEM_CONFIG_2, config_2)); - _TX_CHECK(sx127x_write_register(hndl, REG_FIFO_ADDR_PTR, 0)); - _TX_CHECK(sx127x_write_register(hndl, REG_PAYLOAD_LENGTH, 0)); + _TX_CHECK(sx127x_write_register(hndl, SX127X_REG_FIFO_ADDR_PTR, 0)); + _TX_CHECK(sx127x_write_register(hndl, SX127X_REG_PAYLOAD_LENGTH, 0)); _TX_CHECK(sx127x_write_fifo(hndl, packet->data, packet->data_len)); - _TX_CHECK(sx127x_write_register(hndl, REG_PAYLOAD_LENGTH, packet->data_len)); + _TX_CHECK( + sx127x_write_register(hndl, SX127X_REG_PAYLOAD_LENGTH, packet->data_len)); - _TX_CHECK(sx127x_write_register(hndl, REG_OP_MODE, + _TX_CHECK(sx127x_write_register(hndl, SX127X_REG_OP_MODE, SX127X_LONG_RANGE | SX127X_MODE_FS_TX)); vTaskDelay(pdMS_TO_TICKS(1)); - _TX_CHECK(sx127x_write_register(hndl, REG_OP_MODE, + _TX_CHECK(sx127x_write_register(hndl, SX127X_REG_OP_MODE, SX127X_LONG_RANGE | SX127X_MODE_TX)); // wait for transmission to finish while (true) { - _TX_CHECK(sx127x_read_register(hndl, REG_IRQ_FLAGS, &irq_flags)); - if (irq_flags & IRQ_TX_DONE_MASK) { // if the transmission is done + _TX_CHECK(sx127x_read_register(hndl, SX127X_REG_IRQ_FLAGS, &irq_flags)); + if (irq_flags & SX127X_IRQ_TX_DONE_MASK) { // if the transmission is done break; } vTaskDelay(1); } // clear tx done bit - _TX_CHECK(sx127x_write_register(hndl, REG_IRQ_FLAGS, IRQ_TX_DONE_MASK)); + _TX_CHECK( + sx127x_write_register(hndl, SX127X_REG_IRQ_FLAGS, SX127X_IRQ_TX_DONE_MASK)); error: if (ret != ESP_OK) { @@ -212,7 +216,7 @@ error: ESP_LOGE(SX127X_TAG, "tx error: %s (%d)", error_name, ret); } // go back to rx mode - sx127x_write_register(hndl, REG_OP_MODE, + sx127x_write_register(hndl, SX127X_REG_OP_MODE, SX127X_LONG_RANGE | SX127X_MODE_RX_CONT); } @@ -222,26 +226,26 @@ static void sx127x_do_rx(sx127x_t *hndl) { esp_err_t ret; BaseType_t pdRet; - _TX_CHECK(sx127x_read_register(hndl, REG_IRQ_FLAGS, &irq_flags)); + _TX_CHECK(sx127x_read_register(hndl, SX127X_REG_IRQ_FLAGS, &irq_flags)); // clear irq flags - _TX_CHECK(sx127x_write_register(hndl, REG_IRQ_FLAGS, irq_flags)); + _TX_CHECK(sx127x_write_register(hndl, SX127X_REG_IRQ_FLAGS, irq_flags)); - if (irq_flags & IRQ_PAYLOAD_CRC_ERROR_MASK) { + if (irq_flags & SX127X_IRQ_PAYLOAD_CRC_ERROR_MASK) { ESP_LOGW(SX127X_TAG, "rx crc error"); goto error; } - if ((irq_flags & IRQ_RX_DONE_MASK) == 0) { + if ((irq_flags & SX127X_IRQ_RX_DONE_MASK) == 0) { ESP_LOGD(SX127X_TAG, "sx127x_do_rx called but no rx done"); goto error; } - sx127x_write_register(hndl, REG_OP_MODE, + sx127x_write_register(hndl, SX127X_REG_OP_MODE, SX127X_LONG_RANGE | SX127X_MODE_STDBY); // TODO: implicit header receive? - _TX_CHECK(sx127x_read_register(hndl, REG_RX_NB_BYTES, &packet_len)); - _TX_CHECK( - sx127x_write_register(hndl, REG_FIFO_ADDR_PTR, REG_FIFO_RX_CURRENT_ADDR)); + _TX_CHECK(sx127x_read_register(hndl, SX127X_REG_RX_NB_BYTES, &packet_len)); + _TX_CHECK(sx127x_write_register(hndl, SX127X_REG_FIFO_ADDR_PTR, + SX127X_REG_FIFO_RX_CURRENT_ADDR)); packet.data_len = packet_len; packet.data = heap_caps_malloc( @@ -267,9 +271,9 @@ error: const char *error_name = esp_err_to_name(ret); ESP_LOGE(SX127X_TAG, "rx error: %s (%d)", error_name, ret); } - sx127x_write_register(hndl, REG_FIFO_ADDR_PTR, 0); + sx127x_write_register(hndl, SX127X_REG_FIFO_ADDR_PTR, 0); // go back to rx mode - sx127x_write_register(hndl, REG_OP_MODE, + sx127x_write_register(hndl, SX127X_REG_OP_MODE, SX127X_LONG_RANGE | SX127X_MODE_RX_CONT); } @@ -282,7 +286,7 @@ void sx127x_task(void *arg) { sx127x_packet_t packet; // be in rx mode by default - sx127x_write_register(hndl, REG_OP_MODE, + sx127x_write_register(hndl, SX127X_REG_OP_MODE, SX127X_LONG_RANGE | SX127X_MODE_RX_CONT); while (atomic_load(&hndl->task_state) == SX127X_TASK_RUNNING) { @@ -328,7 +332,7 @@ esp_err_t sx127x_start(sx127x_t *hndl) { (void *)hndl, SX127X_TASK_PRIORITY, &hndl->task_handle); SX127X_CHECK(pdRet == pdPASS, "failed to create task", ESP_FAIL); - ret = sx127x_write_register(hndl, REG_DIO_MAPPING_1, 0x00); + ret = sx127x_write_register(hndl, SX127X_REG_DIO_MAPPING_1, 0x00); SX127X_ERROR_CHECK(ret); gpio_config_t irq_io_config; diff --git a/components/sx127x_driver/sx127x_internal.h b/components/sx127x_driver/sx127x_internal.h index 5ea40f5..0fe6bd5 100644 --- a/components/sx127x_driver/sx127x_internal.h +++ b/components/sx127x_driver/sx127x_internal.h @@ -19,64 +19,7 @@ // 8mhz #define SPI_CLOCK_HZ (8 * 1000 * 1000) -#define REG_FIFO 0x00 -#define REG_OP_MODE 0x01 -#define REG_FRF_MSB 0x06 -#define REG_FRF_MID 0x07 -#define REG_FRF_LSB 0x08 -#define REG_PA_CONFIG 0x09 -#define REG_OCP 0x0b -#define REG_LNA 0x0c -#define REG_FIFO_ADDR_PTR 0x0d -#define REG_FIFO_TX_BASE_ADDR 0x0e -#define REG_FIFO_RX_BASE_ADDR 0x0f -#define REG_FIFO_RX_CURRENT_ADDR 0x10 -#define REG_IRQ_FLAGS 0x12 -#define REG_RX_NB_BYTES 0x13 -#define REG_PKT_SNR_VALUE 0x19 -#define REG_PKT_RSSI_VALUE 0x1a -#define REG_MODEM_CONFIG_1 0x1d -#define REG_MODEM_CONFIG_2 0x1e -#define REG_PREAMBLE_MSB 0x20 -#define REG_PREAMBLE_LSB 0x21 -#define REG_PAYLOAD_LENGTH 0x22 -#define REG_MODEM_CONFIG_3 0x26 -#define REG_FREQ_ERROR_MSB 0x28 -#define REG_FREQ_ERROR_MID 0x29 -#define REG_FREQ_ERROR_LSB 0x2a -#define REG_RSSI_WIDEBAND 0x2c -#define REG_DETECTION_OPTIMIZE 0x31 -#define REG_INVERTIQ 0x33 -#define REG_DETECTION_THRESHOLD 0x37 -#define REG_SYNC_WORD 0x39 -#define REG_INVERTIQ2 0x3b -#define REG_DIO_MAPPING_1 0x40 -#define REG_VERSION 0x42 -#define REG_PA_DAC 0x4d -typedef enum sx127x_op_mode { - SX127X_MODE_SLEEP = 0x00, - SX127X_MODE_STDBY = 0x01, - SX127X_MODE_FS_TX = 0x02, - SX127X_MODE_TX = 0x03, - SX127X_MODE_FS_RX = 0x04, - SX127X_MODE_RX_CONT = 0x05, - SX127X_MODE_RX_SINGLE = 0x06, - SX127X_MODE_CAD = 0x07, - SX127X_MODE = 0x07, - SX127X_LONG_RANGE = (1 << 7) -} sx127x_op_mode_t; - -#define CONFIG2_CRC 0x04 -#define CONFIG3_AUTO_AGC 0x04 - -// PA config -#define PA_BOOST 0x80 - -// IRQ masks -#define IRQ_TX_DONE_MASK 0x08 -#define IRQ_PAYLOAD_CRC_ERROR_MASK 0x20 -#define IRQ_RX_DONE_MASK 0x40 #ifdef NODEBUG #define SX127X_CHECK(check, str, ret_val, ...) \ diff --git a/components/sx127x_driver/sx127x_registers.c b/components/sx127x_driver/sx127x_registers.c index 9791e8f..b3e700c 100644 --- a/components/sx127x_driver/sx127x_registers.c +++ b/components/sx127x_driver/sx127x_registers.c @@ -3,15 +3,17 @@ #include -esp_err_t sx127x_read_register(sx127x_t *hndl, uint8_t reg, uint8_t *value) { +esp_err_t sx127x_read_register(sx127x_t *hndl, sx127x_reg_t reg, + uint8_t *value) { return sx127x_single_transfer(hndl, reg & 0x7f, 0x00, value); } -esp_err_t sx127x_write_register(sx127x_t *hndl, uint8_t reg, uint8_t value) { +esp_err_t sx127x_write_register(sx127x_t *hndl, sx127x_reg_t reg, + uint8_t value) { return sx127x_single_transfer(hndl, reg | 0x80, value, NULL); } -esp_err_t sx127x_single_transfer(sx127x_t *hndl, uint8_t addr, +esp_err_t sx127x_single_transfer(sx127x_t *hndl, sx127x_reg_t addr, uint8_t to_slave, uint8_t *from_slave) { spi_transaction_t trans; memset(&trans, 0, sizeof(trans)); @@ -32,12 +34,12 @@ esp_err_t sx127x_single_transfer(sx127x_t *hndl, uint8_t addr, } esp_err_t sx127x_sleep(sx127x_t *hndl) { - return sx127x_write_register(hndl, REG_OP_MODE, + return sx127x_write_register(hndl, SX127X_REG_OP_MODE, SX127X_LONG_RANGE | SX127X_MODE_SLEEP); } esp_err_t sx127x_standby(sx127x_t *hndl) { - return sx127x_write_register(hndl, REG_OP_MODE, + return sx127x_write_register(hndl, SX127X_REG_OP_MODE, SX127X_LONG_RANGE | SX127X_MODE_STDBY); } @@ -45,13 +47,13 @@ esp_err_t sx127x_set_frequency(sx127x_t *hndl, uint64_t frequency) { uint64_t frf = ((uint64_t)frequency << 19) / 32000000; esp_err_t ret; - ret = sx127x_write_register(hndl, REG_FRF_MSB, (uint8_t)(frf)); + ret = sx127x_write_register(hndl, SX127X_REG_FRF_MSB, (uint8_t)(frf)); SX127X_ERROR_CHECK(ret); frf >>= 8; - ret = sx127x_write_register(hndl, REG_FRF_MID, (uint8_t)(frf)); + ret = sx127x_write_register(hndl, SX127X_REG_FRF_MID, (uint8_t)(frf)); SX127X_ERROR_CHECK(ret); frf >>= 8; - ret = sx127x_write_register(hndl, REG_FRF_LSB, (uint8_t)(frf)); + ret = sx127x_write_register(hndl, SX127X_REG_FRF_LSB, (uint8_t)(frf)); SX127X_ERROR_CHECK(ret); hndl->config.frequency = frequency; @@ -65,13 +67,12 @@ esp_err_t sx127x_set_tx_power(sx127x_t *hndl, uint8_t tx_power, // PA BOOST SX127X_CHECK(tx_power >= 2 && tx_power <= 20, "invalid tx_power: %d", ESP_ERR_INVALID_ARG, tx_power); - ret = - sx127x_write_register(hndl, REG_PA_CONFIG, PA_BOOST | (tx_power - 2)); + ret = sx127x_write_register(hndl, SX127X_REG_PA_CONFIG, SX127X_PA_BOOST | (tx_power - 2)); } else { // RFO SX127X_CHECK(tx_power <= 14, "invalid tx_power: %d", ESP_ERR_INVALID_ARG, tx_power); - ret = sx127x_write_register(hndl, REG_PA_CONFIG, 0x70 | tx_power); + ret = sx127x_write_register(hndl, SX127X_REG_PA_CONFIG, 0x70 | tx_power); } SX127X_ERROR_CHECK(ret); @@ -92,17 +93,17 @@ esp_err_t sx127x_set_spreading_factor(sx127x_t *hndl, detection_optimize = 0xc3; detection_threshold = 0x0a; } - SX127X_ERROR_CHECK(sx127x_write_register(hndl, REG_DETECTION_OPTIMIZE, - detection_optimize)); - SX127X_ERROR_CHECK(sx127x_write_register(hndl, REG_DETECTION_THRESHOLD, + SX127X_ERROR_CHECK( + sx127x_write_register(hndl, SX127X_REG_DETECTION_OPTIMIZE, detection_optimize)); + SX127X_ERROR_CHECK(sx127x_write_register(hndl, SX127X_REG_DETECTION_THRESHOLD, detection_threshold)); uint8_t modem_config_3; SX127X_ERROR_CHECK( - sx127x_read_register(hndl, REG_MODEM_CONFIG_3, &modem_config_3)); + sx127x_read_register(hndl, SX127X_REG_MODEM_CONFIG_3, &modem_config_3)); modem_config_3 = (modem_config_3 & 0x03) | ((spreading_factor << 4) & 0xf0); SX127X_ERROR_CHECK( - sx127x_write_register(hndl, REG_MODEM_CONFIG_3, modem_config_3)); + sx127x_write_register(hndl, SX127X_REG_MODEM_CONFIG_3, modem_config_3)); hndl->config.spreading_factor = spreading_factor; return ESP_OK; @@ -113,10 +114,10 @@ esp_err_t sx127x_set_signal_bandwidth(sx127x_t *hndl, uint8_t bw_reg = sx127x_bw_to_reg(signal_bandwidth); uint8_t modem_config_1; SX127X_ERROR_CHECK( - sx127x_read_register(hndl, REG_MODEM_CONFIG_1, &modem_config_1)); + sx127x_read_register(hndl, SX127X_REG_MODEM_CONFIG_1, &modem_config_1)); modem_config_1 = (modem_config_1 & 0x0f) | (bw_reg << 4); SX127X_ERROR_CHECK( - sx127x_write_register(hndl, REG_MODEM_CONFIG_1, modem_config_1)); + sx127x_write_register(hndl, SX127X_REG_MODEM_CONFIG_1, modem_config_1)); hndl->config.signal_bandwidth = signal_bandwidth; // set low data rate optimization flag @@ -131,14 +132,14 @@ esp_err_t sx127x_set_signal_bandwidth(sx127x_t *hndl, uint8_t modem_config_3; SX127X_ERROR_CHECK( - sx127x_read_register(hndl, REG_MODEM_CONFIG_3, &modem_config_3)); + sx127x_read_register(hndl, SX127X_REG_MODEM_CONFIG_3, &modem_config_3)); if (ldo) { modem_config_3 |= (1 << 3); } else { modem_config_3 &= ~(1 << 3); } SX127X_ERROR_CHECK( - sx127x_write_register(hndl, REG_MODEM_CONFIG_3, modem_config_3)); + sx127x_write_register(hndl, SX127X_REG_MODEM_CONFIG_3, modem_config_3)); return ESP_OK; } @@ -184,7 +185,7 @@ uint64_t sx127x_reg_to_bw(uint8_t bandwidth_reg) { } esp_err_t sx127x_set_sync_word(sx127x_t *hndl, uint8_t sync_word) { - SX127X_ERROR_CHECK(sx127x_write_register(hndl, REG_SYNC_WORD, sync_word)); + SX127X_ERROR_CHECK(sx127x_write_register(hndl, SX127X_REG_SYNC_WORD, sync_word)); hndl->config.sync_word = sync_word; return ESP_OK; } @@ -192,14 +193,14 @@ esp_err_t sx127x_set_sync_word(sx127x_t *hndl, uint8_t sync_word) { esp_err_t sx127x_set_crc(sx127x_t *hndl, sx127x_crc_t crc) { uint8_t modem_config_2; SX127X_ERROR_CHECK( - sx127x_read_register(hndl, REG_MODEM_CONFIG_2, &modem_config_2)); + sx127x_read_register(hndl, SX127X_REG_MODEM_CONFIG_2, &modem_config_2)); if (crc == SX127X_CRC_ENABLED) { - modem_config_2 |= CONFIG2_CRC; + modem_config_2 |= SX127X_CONFIG2_CRC; } else { - modem_config_2 &= ~CONFIG2_CRC; + modem_config_2 &= ~SX127X_CONFIG2_CRC; } SX127X_ERROR_CHECK( - sx127x_write_register(hndl, REG_MODEM_CONFIG_2, modem_config_2)); + sx127x_write_register(hndl, SX127X_REG_MODEM_CONFIG_2, modem_config_2)); hndl->config.crc = crc; return ESP_OK; } @@ -209,8 +210,7 @@ esp_err_t sx127x_read_pkt_rssi(sx127x_t *hndl, int32_t *rssi) { uint8_t rssi_val; uint64_t freq = hndl->config.frequency; int32_t min_rssi = (freq < 868E6) ? -164 : -157; - SX127X_ERROR_CHECK( - sx127x_read_register(hndl, REG_PKT_RSSI_VALUE, &rssi_val)) + SX127X_ERROR_CHECK(sx127x_read_register(hndl, SX127X_REG_PKT_RSSI_VALUE, &rssi_val)) *rssi = min_rssi + rssi_val; return ESP_OK; } @@ -219,17 +219,16 @@ esp_err_t sx127x_read_pkt_snr(sx127x_t *hndl, int8_t *snr) { SX127X_CHECK(snr != NULL, "rssi can not be NULL", ESP_ERR_INVALID_ARG); int8_t snr_val; SX127X_ERROR_CHECK( - sx127x_read_register(hndl, REG_PKT_SNR_VALUE, (uint8_t *)&snr_val)) + sx127x_read_register(hndl, SX127X_REG_PKT_SNR_VALUE, (uint8_t *)&snr_val)) *snr = snr_val; return ESP_OK; } -esp_err_t sx127x_write_fifo(sx127x_t *hndl, const char *data, - size_t data_len) { +esp_err_t sx127x_write_fifo(sx127x_t *hndl, const char *data, size_t data_len) { spi_transaction_t trans; memset(&trans, 0, sizeof(trans)); trans.flags = 0; - trans.addr = REG_FIFO; + trans.addr = SX127X_REG_FIFO; trans.length = 8 * data_len; trans.tx_buffer = data; trans.rxlength = 0; @@ -245,7 +244,7 @@ esp_err_t sx127x_read_fifo(sx127x_t *hndl, char *data_out, size_t data_len) { spi_transaction_t trans; memset(&trans, 0, sizeof(trans)); trans.flags = 0; - trans.addr = REG_FIFO; + trans.addr = SX127X_REG_FIFO; trans.length = 8 * data_len; trans.tx_buffer = NULL; trans.rxlength = 0; // match length diff --git a/components/sx127x_driver/sx127x_registers.h b/components/sx127x_driver/sx127x_registers.h index a872806..334d386 100644 --- a/components/sx127x_driver/sx127x_registers.h +++ b/components/sx127x_driver/sx127x_registers.h @@ -1,8 +1,69 @@ #include "sx127x_driver.h" -esp_err_t sx127x_read_register(sx127x_hndl hdnl, uint8_t reg, uint8_t *value); -esp_err_t sx127x_write_register(sx127x_hndl hdnl, uint8_t reg, uint8_t value); -esp_err_t sx127x_single_transfer(sx127x_hndl hdnl, uint8_t addr, +typedef enum sx127x_reg { + SX127X_REG_FIFO = 0x00, + SX127X_REG_OP_MODE = 0x01, + SX127X_REG_FRF_MSB = 0x06, + SX127X_REG_FRF_MID = 0x07, + SX127X_REG_FRF_LSB = 0x08, + SX127X_REG_PA_CONFIG = 0x09, + SX127X_REG_OCP = 0x0b, + SX127X_REG_LNA = 0x0c, + SX127X_REG_FIFO_ADDR_PTR = 0x0d, + SX127X_REG_FIFO_TX_BASE_ADDR = 0x0e, + SX127X_REG_FIFO_RX_BASE_ADDR = 0x0f, + SX127X_REG_FIFO_RX_CURRENT_ADDR = 0x10, + SX127X_REG_IRQ_FLAGS = 0x12, + SX127X_REG_RX_NB_BYTES = 0x13, + SX127X_REG_PKT_SNR_VALUE = 0x19, + SX127X_REG_PKT_RSSI_VALUE = 0x1a, + SX127X_REG_MODEM_CONFIG_1 = 0x1d, + SX127X_REG_MODEM_CONFIG_2 = 0x1e, + SX127X_REG_PREAMBLE_MSB = 0x20, + SX127X_REG_PREAMBLE_LSB = 0x21, + SX127X_REG_PAYLOAD_LENGTH = 0x22, + SX127X_REG_MODEM_CONFIG_3 = 0x26, + SX127X_REG_FREQ_ERROR_MSB = 0x28, + SX127X_REG_FREQ_ERROR_MID = 0x29, + SX127X_REG_FREQ_ERROR_LSB = 0x2a, + SX127X_REG_RSSI_WIDEBAND = 0x2c, + SX127X_REG_DETECTION_OPTIMIZE = 0x31, + SX127X_REG_INVERTIQ = 0x33, + SX127X_REG_DETECTION_THRESHOLD = 0x37, + SX127X_REG_SYNC_WORD = 0x39, + SX127X_REG_INVERTIQ2 = 0x3b, + SX127X_REG_DIO_MAPPING_1 = 0x40, + SX127X_REG_VERSION = 0x42, + SX127X_REG_PA_DAC = 0x4d, +} sx127x_reg_t; + +typedef enum sx127x_op_mode { + SX127X_MODE_SLEEP = 0x00, + SX127X_MODE_STDBY = 0x01, + SX127X_MODE_FS_TX = 0x02, + SX127X_MODE_TX = 0x03, + SX127X_MODE_FS_RX = 0x04, + SX127X_MODE_RX_CONT = 0x05, + SX127X_MODE_RX_SINGLE = 0x06, + SX127X_MODE_CAD = 0x07, + SX127X_MODE = 0x07, + SX127X_LONG_RANGE = (1 << 7) +} sx127x_op_mode_t; + +#define SX127X_CONFIG2_CRC 0x04 +#define SX127X_CONFIG3_AUTO_AGC 0x04 + +// PA config +#define SX127X_PA_BOOST 0x80 + +// IRQ masks +#define SX127X_IRQ_TX_DONE_MASK 0x08 +#define SX127X_IRQ_PAYLOAD_CRC_ERROR_MASK 0x20 +#define SX127X_IRQ_RX_DONE_MASK 0x40 + +esp_err_t sx127x_read_register(sx127x_hndl hdnl, sx127x_reg_t reg, uint8_t *value); +esp_err_t sx127x_write_register(sx127x_hndl hdnl, sx127x_reg_t reg, uint8_t value); +esp_err_t sx127x_single_transfer(sx127x_hndl hdnl, sx127x_reg_t addr, uint8_t to_slave, uint8_t *from_slave); esp_err_t sx127x_sleep(sx127x_hndl hdnl);